完成HLS中的工作后，需要导出IP核到vivado中。

可以在solution1\syn\report文件夹中LeNet_csynth.rpt文件查看资源使用率，不超过100%即可吧。

导出IP核到block design这一部分我看的是正点原子的教程，很详细，包括有个文件替换。

4_【正点原子】领航者ZYNQ之Vitis+HLS开发指南_V1.0.pdf(官网就可以下载)

导入IP核后，要进行bd设计：

在这里先把这些IP核都导进来，可以先对ZYNQ这个核做一下设置，双击它之后，我按正点原子给的教程配置sd卡和uart，在vitis中实践没有成功，而是找到了一个tcl文件，把他按照下图配置完，把多余的端口去掉，少掉的端口补上，完成的sd卡读写和uart通信。

tcl文件内容：可以自己创建一个叫做PZ_ZYNQ_Config.tcl文件，然后把以下内容粘贴进去，应该可以，我没试过。这个文件是我这款开发板资料里有的。

proc getPresetInfo {} {
  return [dict create name {PZ_ZYNQ_Config.tcl} description {PZ_ZYNQ_Config.tcl}  vlnv xilinx.com:ip:processing_system7:5.5 display_name {PZ_ZYNQ_Config.tcl} ]
}

proc validate_preset {IPINST} { return true }


proc apply_preset {IPINST} {
  return [dict create \
    CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000}  \
    CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF}  \
    CONFIG.PCW_UART0_BASEADDR {0xE0000000}  \
    CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF}  \
    CONFIG.PCW_UART1_BASEADDR {0xE0001000}  \
    CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF}  \
    CONFIG.PCW_I2C0_BASEADDR {0xE0004000}  \
    CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF}  \
    CONFIG.PCW_I2C1_BASEADDR {0xE0005000}  \
    CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF}  \
    CONFIG.PCW_SPI0_BASEADDR {0xE0006000}  \
    CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF}  \
    CONFIG.PCW_SPI1_BASEADDR {0xE0007000}  \
    CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF}  \
    CONFIG.PCW_CAN0_BASEADDR {0xE0008000}  \
    CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF}  \
    CONFIG.PCW_CAN1_BASEADDR {0xE0009000}  \
    CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF}  \
    CONFIG.PCW_GPIO_BASEADDR {0xE000A000}  \
    CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF}  \
    CONFIG.PCW_ENET0_BASEADDR {0xE000B000}  \
    CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF}  \
    CONFIG.PCW_ENET1_BASEADDR {0xE000C000}  \
    CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF}  \
    CONFIG.PCW_SDIO0_BASEADDR {0xE0100000}  \
    CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF}  \
    CONFIG.PCW_SDIO1_BASEADDR {0xE0101000}  \
    CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF}  \
    CONFIG.PCW_USB0_BASEADDR {0xE0102000}  \
    CONFIG.PCW_USB0_HIGHADDR {0xE0102fff}  \
    CONFIG.PCW_USB1_BASEADDR {0xE0103000}  \
    CONFIG.PCW_USB1_HIGHADDR {0xE0103fff}  \
    CONFIG.PCW_TTC0_BASEADDR {0xE0104000}  \
    CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff}  \
    CONFIG.PCW_TTC1_BASEADDR {0xE0105000}  \
    CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff}  \
    CONFIG.PCW_FCLK_CLK0_BUF {FALSE}  \
    CONFIG.PCW_FCLK_CLK1_BUF {FALSE}  \
    CONFIG.PCW_FCLK_CLK2_BUF {FALSE}  \
    CONFIG.PCW_FCLK_CLK3_BUF {FALSE}  \
    CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333}  \
    CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3}  \
    CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15}  \
    CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10}  \
    CONFIG.PCW_UIPARAM_DDR_CL {7}  \
    CONFIG.PCW_UIPARAM_DDR_CWL {6}  \
    CONFIG.PCW_UIPARAM_DDR_T_RCD {7}  \
    CONFIG.PCW_UIPARAM_DDR_T_RP {7}  \
    CONFIG.PCW_UIPARAM_DDR_T_RC {48.75}  \
    CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}  \
    CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}  \
    CONFIG.PCW_UIPARAM_DDR_AL {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0}  \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25}  \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25}  \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25}  \
    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160}  \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.025}  \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.014}  \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009}  \
    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033}  \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.089}  \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.075}  \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085}  \
    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092}  \
    CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {767}  \
    CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333}  \
    CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {767}  \
    CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159}  \
    CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200}  \
    CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100}  \
    CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60}  \
    CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60}  \
    CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100}  \
    CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100}  \
    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666}  \
    CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100}  \
    CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1}  \
    CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1}  \
    CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25}  \
    CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50}  \
    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333}  \
    CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200}  \
    CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200}  \
    CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100}  \
    CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {125}  \
    CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200}  \
    CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50}  \
    CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {766.666687}  \
    CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374}  \
    CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730}  \
    CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000}  \
    CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000}  \
    CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000}  \
    CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000}  \
    CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60}  \
    CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60}  \
    CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000}  \
    CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000}  \
    CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000}  \
    CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {100.000000}  \
    CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095}  \
    CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095}  \
    CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50}  \
    CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50}  \
    CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000}  \
    CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000}  \
    CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000}  \
    CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000}  \
    CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000}  \
    CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000}  \
    CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {127.777786}  \
    CONFIG.PCW_CLK0_FREQ {100000000}  \
    CONFIG.PCW_CLK1_FREQ {10000000}  \
    CONFIG.PCW_CLK2_FREQ {10000000}  \
    CONFIG.PCW_CLK3_FREQ {10000000}  \
    CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0}  \
    CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2}  \
    CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2}  \
    CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5}  \
    CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10}  \
    CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10}  \
    CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {5}  \
    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {2}  \
    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5}  \
    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2}  \
    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1}  \
    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1}  \
    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1}  \
    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8}  \
    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1}  \
    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1}  \
    CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15}  \
    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7}  \
    CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5}  \
    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1}  \
    CONFIG.PCW_ARMPLL_CTRL_FBDIV {46}  \
    CONFIG.PCW_IOPLL_CTRL_FBDIV {30}  \
    CONFIG.PCW_DDRPLL_CTRL_FBDIV {32}  \
    CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1533.333}  \
    CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000}  \
    CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667}  \
    CONFIG.PCW_SMC_PERIPHERAL_VALID {0}  \
    CONFIG.PCW_SDIO_PERIPHERAL_VALID {1}  \
    CONFIG.PCW_SPI_PERIPHERAL_VALID {0}  \
    CONFIG.PCW_CAN_PERIPHERAL_VALID {1}  \
    CONFIG.PCW_UART_PERIPHERAL_VALID {1}  \
    CONFIG.PCW_EN_EMIO_CAN0 {0}  \
    CONFIG.PCW_EN_EMIO_CAN1 {0}  \
    CONFIG.PCW_EN_EMIO_ENET0 {0}  \
    CONFIG.PCW_EN_EMIO_ENET1 {0}  \
    CONFIG.PCW_EN_PTP_ENET0 {0}  \
    CONFIG.PCW_EN_PTP_ENET1 {0}  \
    CONFIG.PCW_EN_EMIO_GPIO {1}  \
    CONFIG.PCW_EN_EMIO_I2C0 {0}  \
    CONFIG.PCW_EN_EMIO_I2C1 {0}  \
    CONFIG.PCW_EN_EMIO_PJTAG {0}  \
    CONFIG.PCW_EN_EMIO_SDIO0 {0}  \
    CONFIG.PCW_EN_EMIO_CD_SDIO0 {0}  \
    CONFIG.PCW_EN_EMIO_WP_SDIO0 {0}  \
    CONFIG.PCW_EN_EMIO_SDIO1 {0}  \
    CONFIG.PCW_EN_EMIO_CD_SDIO1 {0}  \
    CONFIG.PCW_EN_EMIO_WP_SDIO1 {0}  \
    CONFIG.PCW_EN_EMIO_SPI0 {0}  \
    CONFIG.PCW_EN_EMIO_SPI1 {0}  \
    CONFIG.PCW_EN_EMIO_UART0 {0}  \
    CONFIG.PCW_EN_EMIO_UART1 {0}  \
    CONFIG.PCW_EN_EMIO_MODEM_UART0 {0}  \
    CONFIG.PCW_EN_EMIO_MODEM_UART1 {0}  \
    CONFIG.PCW_EN_EMIO_TTC0 {0}  \
    CONFIG.PCW_EN_EMIO_TTC1 {0}  \
    CONFIG.PCW_EN_EMIO_WDT {0}  \
    CONFIG.PCW_EN_EMIO_TRACE {0}  \
    CONFIG.PCW_USE_AXI_NONSECURE {0}  \
    CONFIG.PCW_USE_M_AXI_GP0 {0}  \
    CONFIG.PCW_USE_M_AXI_GP1 {0}  \
    CONFIG.PCW_USE_S_AXI_GP0 {0}  \
    CONFIG.PCW_USE_S_AXI_GP1 {0}  \
    CONFIG.PCW_USE_S_AXI_ACP {0}  \
    CONFIG.PCW_USE_S_AXI_HP0 {0}  \
    CONFIG.PCW_USE_S_AXI_HP1 {0}  \
    CONFIG.PCW_USE_S_AXI_HP2 {0}  \
    CONFIG.PCW_USE_S_AXI_HP3 {0}  \
    CONFIG.PCW_USE_DMA0 {0}  \
    CONFIG.PCW_USE_DMA1 {0}  \
    CONFIG.PCW_USE_DMA2 {0}  \
    CONFIG.PCW_USE_DMA3 {0}  \
    CONFIG.PCW_USE_TRACE {0}  \
    CONFIG.PCW_TRACE_PIPELINE_WIDTH {8}  \
    CONFIG.PCW_INCLUDE_TRACE_BUFFER {0}  \
    CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128}  \
    CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0}  \
    CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12}  \
    CONFIG.PCW_USE_CROSS_TRIGGER {0}  \
    CONFIG.PCW_FTM_CTI_IN0 {<Select>}  \
    CONFIG.PCW_FTM_CTI_IN1 {<Select>}  \
    CONFIG.PCW_FTM_CTI_IN2 {<Select>}  \
    CONFIG.PCW_FTM_CTI_IN3 {<Select>}  \
    CONFIG.PCW_FTM_CTI_OUT0 {<Select>}  \
    CONFIG.PCW_FTM_CTI_OUT1 {<Select>}  \
    CONFIG.PCW_FTM_CTI_OUT2 {<Select>}  \
    CONFIG.PCW_FTM_CTI_OUT3 {<Select>}  \
    CONFIG.PCW_USE_DEBUG {0}  \
    CONFIG.PCW_USE_CR_FABRIC {1}  \
    CONFIG.PCW_USE_AXI_FABRIC_IDLE {0}  \
    CONFIG.PCW_USE_DDR_BYPASS {0}  \
    CONFIG.PCW_USE_FABRIC_INTERRUPT {0}  \
    CONFIG.PCW_USE_PROC_EVENT_BUS {0}  \
    CONFIG.PCW_USE_EXPANDED_IOP {0}  \
    CONFIG.PCW_USE_HIGH_OCM {0}  \
    CONFIG.PCW_USE_PS_SLCR_REGISTERS {0}  \
    CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0}  \
    CONFIG.PCW_USE_CORESIGHT {0}  \
    CONFIG.PCW_EN_EMIO_SRAM_INT {0}  \
    CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {3}  \
    CONFIG.PCW_GP0_NUM_WRITE_THREADS {4}  \
    CONFIG.PCW_GP0_NUM_READ_THREADS {4}  \
    CONFIG.PCW_GP1_NUM_WRITE_THREADS {4}  \
    CONFIG.PCW_GP1_NUM_READ_THREADS {4}  \
    CONFIG.PCW_UART0_BAUD_RATE {115200}  \
    CONFIG.PCW_UART1_BAUD_RATE {115200}  \
    CONFIG.PCW_EN_4K_TIMER {0}  \
    CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12}  \
    CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0}  \
    CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0}  \
    CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12}  \
    CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12}  \
    CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0}  \
    CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0}  \
    CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12}  \
    CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6}  \
    CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6}  \
    CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3}  \
    CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0}  \
    CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0}  \
    CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31}  \
    CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31}  \
    CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6}  \
    CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64}  \
    CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6}  \
    CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64}  \
    CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6}  \
    CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64}  \
    CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6}  \
    CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64}  \
    CONFIG.PCW_EN_DDR {1}  \
    CONFIG.PCW_EN_SMC {0}  \
    CONFIG.PCW_EN_QSPI {1}  \
    CONFIG.PCW_EN_CAN0 {1}  \
    CONFIG.PCW_EN_CAN1 {0}  \
    CONFIG.PCW_EN_ENET0 {1}  \
    CONFIG.PCW_EN_ENET1 {0}  \
    CONFIG.PCW_EN_GPIO {1}  \
    CONFIG.PCW_EN_I2C0 {0}  \
    CONFIG.PCW_EN_I2C1 {0}  \
    CONFIG.PCW_EN_PJTAG {0}  \
    CONFIG.PCW_EN_SDIO0 {1}  \
    CONFIG.PCW_EN_SDIO1 {0}  \
    CONFIG.PCW_EN_SPI0 {0}  \
    CONFIG.PCW_EN_SPI1 {0}  \
    CONFIG.PCW_EN_UART0 {1}  \
    CONFIG.PCW_EN_UART1 {1}  \
    CONFIG.PCW_EN_MODEM_UART0 {0}  \
    CONFIG.PCW_EN_MODEM_UART1 {0}  \
    CONFIG.PCW_EN_TTC0 {0}  \
    CONFIG.PCW_EN_TTC1 {0}  \
    CONFIG.PCW_EN_WDT {0}  \
    CONFIG.PCW_EN_TRACE {0}  \
    CONFIG.PCW_EN_USB0 {1}  \
    CONFIG.PCW_EN_USB1 {0}  \
    CONFIG.PCW_DQ_WIDTH {32}  \
    CONFIG.PCW_DQS_WIDTH {4}  \
    CONFIG.PCW_DM_WIDTH {4}  \
    CONFIG.PCW_MIO_PRIMITIVE {54}  \
    CONFIG.PCW_EN_CLK0_PORT {1}  \
    CONFIG.PCW_EN_CLK1_PORT {0}  \
    CONFIG.PCW_EN_CLK2_PORT {0}  \
    CONFIG.PCW_EN_CLK3_PORT {0}  \
    CONFIG.PCW_EN_RST0_PORT {1}  \
    CONFIG.PCW_EN_RST1_PORT {0}  \
    CONFIG.PCW_EN_RST2_PORT {0}  \
    CONFIG.PCW_EN_RST3_PORT {0}  \
    CONFIG.PCW_EN_CLKTRIG0_PORT {0}  \
    CONFIG.PCW_EN_CLKTRIG1_PORT {0}  \
    CONFIG.PCW_EN_CLKTRIG2_PORT {0}  \
    CONFIG.PCW_EN_CLKTRIG3_PORT {0}  \
    CONFIG.PCW_P2F_DMAC_ABORT_INTR {0}  \
    CONFIG.PCW_P2F_DMAC0_INTR {0}  \
    CONFIG.PCW_P2F_DMAC1_INTR {0}  \
    CONFIG.PCW_P2F_DMAC2_INTR {0}  \
    CONFIG.PCW_P2F_DMAC3_INTR {0}  \
    CONFIG.PCW_P2F_DMAC4_INTR {0}  \
    CONFIG.PCW_P2F_DMAC5_INTR {0}  \
    CONFIG.PCW_P2F_DMAC6_INTR {0}  \
    CONFIG.PCW_P2F_DMAC7_INTR {0}  \
    CONFIG.PCW_P2F_SMC_INTR {0}  \
    CONFIG.PCW_P2F_QSPI_INTR {0}  \
    CONFIG.PCW_P2F_CTI_INTR {0}  \
    CONFIG.PCW_P2F_GPIO_INTR {0}  \
    CONFIG.PCW_P2F_USB0_INTR {0}  \
    CONFIG.PCW_P2F_ENET0_INTR {0}  \
    CONFIG.PCW_P2F_SDIO0_INTR {0}  \
    CONFIG.PCW_P2F_I2C0_INTR {0}  \
    CONFIG.PCW_P2F_SPI0_INTR {0}  \
    CONFIG.PCW_P2F_UART0_INTR {0}  \
    CONFIG.PCW_P2F_CAN0_INTR {0}  \
    CONFIG.PCW_P2F_USB1_INTR {0}  \
    CONFIG.PCW_P2F_ENET1_INTR {0}  \
    CONFIG.PCW_P2F_SDIO1_INTR {0}  \
    CONFIG.PCW_P2F_I2C1_INTR {0}  \
    CONFIG.PCW_P2F_SPI1_INTR {0}  \
    CONFIG.PCW_P2F_UART1_INTR {0}  \
    CONFIG.PCW_P2F_CAN1_INTR {0}  \
    CONFIG.PCW_IRQ_F2P_INTR {1}  \
    CONFIG.PCW_IRQ_F2P_MODE {DIRECT}  \
    CONFIG.PCW_CORE0_FIQ_INTR {0}  \
    CONFIG.PCW_CORE0_IRQ_INTR {0}  \
    CONFIG.PCW_CORE1_FIQ_INTR {0}  \
    CONFIG.PCW_CORE1_IRQ_INTR {0}  \
    CONFIG.PCW_VALUE_SILVERSION {3}  \
    CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1}  \
    CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1}  \
    CONFIG.PCW_IMPORT_BOARD_PRESET {None}  \
    CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None}  \
    CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}  \
    CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}  \
    CONFIG.PCW_UIPARAM_DDR_ENABLE {1}  \
    CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0}  \
    CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)}  \
    CONFIG.PCW_UIPARAM_DDR_ECC {Disabled}  \
    CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}  \
    CONFIG.PCW_UIPARAM_DDR_BL {8}  \
    CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)}  \
    CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}  \
    CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}  \
    CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}  \
    CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F}  \
    CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}  \
    CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}  \
    CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}  \
    CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0}  \
    CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}  \
    CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0}  \
    CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0}  \
    CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0}  \
    CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0}  \
    CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)}  \
    CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2}  \
    CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15}  \
    CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2}  \
    CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_NAND_NAND_IO {<Select>}  \
    CONFIG.PCW_NAND_GRP_D8_ENABLE {0}  \
    CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_NOR_GRP_A25_ENABLE {0}  \
    CONFIG.PCW_NOR_GRP_CS0_ENABLE {0}  \
    CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0}  \
    CONFIG.PCW_NOR_GRP_CS1_ENABLE {0}  \
    CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0}  \
    CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0}  \
    CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6}  \
    CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}  \
    CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6}  \
    CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0}  \
    CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4}  \
    CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0}  \
    CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1}  \
    CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8}  \
    CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF}  \
    CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}  \
    CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}  \
    CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}  \
    CONFIG.PCW_ENET_RESET_ENABLE {1}  \
    CONFIG.PCW_ENET_RESET_SELECT {Share reset pin}  \
    CONFIG.PCW_ENET0_RESET_ENABLE {1}  \
    CONFIG.PCW_ENET0_RESET_IO {MIO 7}  \
    CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0}  \
    CONFIG.PCW_ENET1_RESET_ENABLE {0}  \
    CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}  \
    CONFIG.PCW_SD0_GRP_CD_ENABLE {0}  \
    CONFIG.PCW_SD0_GRP_CD_IO {<Select>}  \
    CONFIG.PCW_SD0_GRP_WP_ENABLE {0}  \
    CONFIG.PCW_SD0_GRP_WP_IO {<Select>}  \
    CONFIG.PCW_SD0_GRP_POW_ENABLE {0}  \
    CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_SD1_SD1_IO {<Select>}  \
    CONFIG.PCW_SD1_GRP_CD_ENABLE {0}  \
    CONFIG.PCW_SD1_GRP_WP_ENABLE {0}  \
    CONFIG.PCW_SD1_GRP_POW_ENABLE {0}  \
    CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47}  \
    CONFIG.PCW_UART0_GRP_FULL_ENABLE {0}  \
    CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49}  \
    CONFIG.PCW_UART1_GRP_FULL_ENABLE {0}  \
    CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0}  \
    CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0}  \
    CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0}  \
    CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0}  \
    CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0}  \
    CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0}  \
    CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_CAN0_CAN0_IO {MIO 50 .. 51}  \
    CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0}  \
    CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0}  \
    CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0}  \
    CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0}  \
    CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0}  \
    CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0}  \
    CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0}  \
    CONFIG.PCW_TRACE_INTERNAL_WIDTH {2}  \
    CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}  \
    CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}  \
    CONFIG.PCW_USB_RESET_ENABLE {1}  \
    CONFIG.PCW_USB_RESET_SELECT {Share reset pin}  \
    CONFIG.PCW_USB0_RESET_ENABLE {1}  \
    CONFIG.PCW_USB0_RESET_IO {MIO 11}  \
    CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_USB1_RESET_ENABLE {0}  \
    CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_I2C0_GRP_INT_ENABLE {0}  \
    CONFIG.PCW_I2C0_RESET_ENABLE {0}  \
    CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_I2C1_GRP_INT_ENABLE {0}  \
    CONFIG.PCW_I2C_RESET_ENABLE {0}  \
    CONFIG.PCW_I2C1_RESET_ENABLE {0}  \
    CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0}  \
    CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}  \
    CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}  \
    CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}  \
    CONFIG.PCW_GPIO_EMIO_GPIO_IO {3}  \
    CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1}  \
    CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps}  \
    CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps}  \
    CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL}  \
    CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL}  \
    CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External}  \
    CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External}  \
    CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External}  \
    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X}  \
    CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL}  \
    CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL}  \
    CONFIG.PCW_USB_RESET_POLARITY {Active Low}  \
    CONFIG.PCW_ENET_RESET_POLARITY {Active Low}  \
    CONFIG.PCW_I2C_RESET_POLARITY {Active Low}  \
    CONFIG.PCW_MIO_0_PULLUP {enabled}  \
    CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_0_DIRECTION {inout}  \
    CONFIG.PCW_MIO_0_SLEW {slow}  \
    CONFIG.PCW_MIO_1_PULLUP {enabled}  \
    CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_1_DIRECTION {out}  \
    CONFIG.PCW_MIO_1_SLEW {slow}  \
    CONFIG.PCW_MIO_2_PULLUP {disabled}  \
    CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_2_DIRECTION {inout}  \
    CONFIG.PCW_MIO_2_SLEW {slow}  \
    CONFIG.PCW_MIO_3_PULLUP {disabled}  \
    CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_3_DIRECTION {inout}  \
    CONFIG.PCW_MIO_3_SLEW {slow}  \
    CONFIG.PCW_MIO_4_PULLUP {disabled}  \
    CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_4_DIRECTION {inout}  \
    CONFIG.PCW_MIO_4_SLEW {slow}  \
    CONFIG.PCW_MIO_5_PULLUP {disabled}  \
    CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_5_DIRECTION {inout}  \
    CONFIG.PCW_MIO_5_SLEW {slow}  \
    CONFIG.PCW_MIO_6_PULLUP {disabled}  \
    CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_6_DIRECTION {out}  \
    CONFIG.PCW_MIO_6_SLEW {slow}  \
    CONFIG.PCW_MIO_7_PULLUP {disabled}  \
    CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_7_DIRECTION {out}  \
    CONFIG.PCW_MIO_7_SLEW {slow}  \
    CONFIG.PCW_MIO_8_PULLUP {disabled}  \
    CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_8_DIRECTION {out}  \
    CONFIG.PCW_MIO_8_SLEW {slow}  \
    CONFIG.PCW_MIO_9_PULLUP {enabled}  \
    CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_9_DIRECTION {inout}  \
    CONFIG.PCW_MIO_9_SLEW {slow}  \
    CONFIG.PCW_MIO_10_PULLUP {enabled}  \
    CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_10_DIRECTION {inout}  \
    CONFIG.PCW_MIO_10_SLEW {slow}  \
    CONFIG.PCW_MIO_11_PULLUP {enabled}  \
    CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_11_DIRECTION {out}  \
    CONFIG.PCW_MIO_11_SLEW {slow}  \
    CONFIG.PCW_MIO_12_PULLUP {enabled}  \
    CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_12_DIRECTION {inout}  \
    CONFIG.PCW_MIO_12_SLEW {slow}  \
    CONFIG.PCW_MIO_13_PULLUP {enabled}  \
    CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_13_DIRECTION {inout}  \
    CONFIG.PCW_MIO_13_SLEW {slow}  \
    CONFIG.PCW_MIO_14_PULLUP {enabled}  \
    CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_14_DIRECTION {inout}  \
    CONFIG.PCW_MIO_14_SLEW {slow}  \
    CONFIG.PCW_MIO_15_PULLUP {enabled}  \
    CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V}  \
    CONFIG.PCW_MIO_15_DIRECTION {inout}  \
    CONFIG.PCW_MIO_15_SLEW {slow}  \
    CONFIG.PCW_MIO_16_PULLUP {enabled}  \
    CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_16_DIRECTION {out}  \
    CONFIG.PCW_MIO_16_SLEW {slow}  \
    CONFIG.PCW_MIO_17_PULLUP {enabled}  \
    CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_17_DIRECTION {out}  \
    CONFIG.PCW_MIO_17_SLEW {slow}  \
    CONFIG.PCW_MIO_18_PULLUP {enabled}  \
    CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_18_DIRECTION {out}  \
    CONFIG.PCW_MIO_18_SLEW {slow}  \
    CONFIG.PCW_MIO_19_PULLUP {enabled}  \
    CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_19_DIRECTION {out}  \
    CONFIG.PCW_MIO_19_SLEW {slow}  \
    CONFIG.PCW_MIO_20_PULLUP {enabled}  \
    CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_20_DIRECTION {out}  \
    CONFIG.PCW_MIO_20_SLEW {slow}  \
    CONFIG.PCW_MIO_21_PULLUP {enabled}  \
    CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_21_DIRECTION {out}  \
    CONFIG.PCW_MIO_21_SLEW {slow}  \
    CONFIG.PCW_MIO_22_PULLUP {enabled}  \
    CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_22_DIRECTION {in}  \
    CONFIG.PCW_MIO_22_SLEW {slow}  \
    CONFIG.PCW_MIO_23_PULLUP {enabled}  \
    CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_23_DIRECTION {in}  \
    CONFIG.PCW_MIO_23_SLEW {slow}  \
    CONFIG.PCW_MIO_24_PULLUP {enabled}  \
    CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_24_DIRECTION {in}  \
    CONFIG.PCW_MIO_24_SLEW {slow}  \
    CONFIG.PCW_MIO_25_PULLUP {enabled}  \
    CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_25_DIRECTION {in}  \
    CONFIG.PCW_MIO_25_SLEW {slow}  \
    CONFIG.PCW_MIO_26_PULLUP {enabled}  \
    CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_26_DIRECTION {in}  \
    CONFIG.PCW_MIO_26_SLEW {slow}  \
    CONFIG.PCW_MIO_27_PULLUP {enabled}  \
    CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_27_DIRECTION {in}  \
    CONFIG.PCW_MIO_27_SLEW {slow}  \
    CONFIG.PCW_MIO_28_PULLUP {enabled}  \
    CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_28_DIRECTION {inout}  \
    CONFIG.PCW_MIO_28_SLEW {slow}  \
    CONFIG.PCW_MIO_29_PULLUP {enabled}  \
    CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_29_DIRECTION {in}  \
    CONFIG.PCW_MIO_29_SLEW {slow}  \
    CONFIG.PCW_MIO_30_PULLUP {enabled}  \
    CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_30_DIRECTION {out}  \
    CONFIG.PCW_MIO_30_SLEW {slow}  \
    CONFIG.PCW_MIO_31_PULLUP {enabled}  \
    CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_31_DIRECTION {in}  \
    CONFIG.PCW_MIO_31_SLEW {slow}  \
    CONFIG.PCW_MIO_32_PULLUP {enabled}  \
    CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_32_DIRECTION {inout}  \
    CONFIG.PCW_MIO_32_SLEW {slow}  \
    CONFIG.PCW_MIO_33_PULLUP {enabled}  \
    CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_33_DIRECTION {inout}  \
    CONFIG.PCW_MIO_33_SLEW {slow}  \
    CONFIG.PCW_MIO_34_PULLUP {enabled}  \
    CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_34_DIRECTION {inout}  \
    CONFIG.PCW_MIO_34_SLEW {slow}  \
    CONFIG.PCW_MIO_35_PULLUP {enabled}  \
    CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_35_DIRECTION {inout}  \
    CONFIG.PCW_MIO_35_SLEW {slow}  \
    CONFIG.PCW_MIO_36_PULLUP {enabled}  \
    CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_36_DIRECTION {in}  \
    CONFIG.PCW_MIO_36_SLEW {slow}  \
    CONFIG.PCW_MIO_37_PULLUP {enabled}  \
    CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_37_DIRECTION {inout}  \
    CONFIG.PCW_MIO_37_SLEW {slow}  \
    CONFIG.PCW_MIO_38_PULLUP {enabled}  \
    CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_38_DIRECTION {inout}  \
    CONFIG.PCW_MIO_38_SLEW {slow}  \
    CONFIG.PCW_MIO_39_PULLUP {enabled}  \
    CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_39_DIRECTION {inout}  \
    CONFIG.PCW_MIO_39_SLEW {slow}  \
    CONFIG.PCW_MIO_40_PULLUP {enabled}  \
    CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_40_DIRECTION {inout}  \
    CONFIG.PCW_MIO_40_SLEW {slow}  \
    CONFIG.PCW_MIO_41_PULLUP {enabled}  \
    CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_41_DIRECTION {inout}  \
    CONFIG.PCW_MIO_41_SLEW {slow}  \
    CONFIG.PCW_MIO_42_PULLUP {enabled}  \
    CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_42_DIRECTION {inout}  \
    CONFIG.PCW_MIO_42_SLEW {slow}  \
    CONFIG.PCW_MIO_43_PULLUP {enabled}  \
    CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_43_DIRECTION {inout}  \
    CONFIG.PCW_MIO_43_SLEW {slow}  \
    CONFIG.PCW_MIO_44_PULLUP {enabled}  \
    CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_44_DIRECTION {inout}  \
    CONFIG.PCW_MIO_44_SLEW {slow}  \
    CONFIG.PCW_MIO_45_PULLUP {enabled}  \
    CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_45_DIRECTION {inout}  \
    CONFIG.PCW_MIO_45_SLEW {slow}  \
    CONFIG.PCW_MIO_46_PULLUP {enabled}  \
    CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_46_DIRECTION {in}  \
    CONFIG.PCW_MIO_46_SLEW {slow}  \
    CONFIG.PCW_MIO_47_PULLUP {enabled}  \
    CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_47_DIRECTION {out}  \
    CONFIG.PCW_MIO_47_SLEW {slow}  \
    CONFIG.PCW_MIO_48_PULLUP {enabled}  \
    CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_48_DIRECTION {out}  \
    CONFIG.PCW_MIO_48_SLEW {slow}  \
    CONFIG.PCW_MIO_49_PULLUP {enabled}  \
    CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_49_DIRECTION {in}  \
    CONFIG.PCW_MIO_49_SLEW {slow}  \
    CONFIG.PCW_MIO_50_PULLUP {enabled}  \
    CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_50_DIRECTION {in}  \
    CONFIG.PCW_MIO_50_SLEW {slow}  \
    CONFIG.PCW_MIO_51_PULLUP {enabled}  \
    CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_51_DIRECTION {out}  \
    CONFIG.PCW_MIO_51_SLEW {slow}  \
    CONFIG.PCW_MIO_52_PULLUP {enabled}  \
    CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_52_DIRECTION {out}  \
    CONFIG.PCW_MIO_52_SLEW {slow}  \
    CONFIG.PCW_MIO_53_PULLUP {enabled}  \
    CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V}  \
    CONFIG.PCW_MIO_53_DIRECTION {inout}  \
    CONFIG.PCW_MIO_53_SLEW {slow}  \
    CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA}  \
    CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#ENET Reset#Quad SPI Flash#GPIO#GPIO#USB Reset#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 0#UART 0#UART 1#UART 1#CAN 0#CAN 0#Enet 0#Enet 0}  \
    CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#qspi_fbclk#gpio[9]#gpio[10]#reset#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#tx#rx#rx#tx#mdc#mdio}  \
    CONFIG.PCW_PS7_SI_REV {PRODUCTION}  \
    CONFIG.PCW_FPGA_FCLK0_ENABLE {1}  \
    CONFIG.PCW_FPGA_FCLK1_ENABLE {0}  \
    CONFIG.PCW_FPGA_FCLK2_ENABLE {0}  \
    CONFIG.PCW_FPGA_FCLK3_ENABLE {0}  \
    CONFIG.PCW_NOR_SRAM_CS0_T_TR {1}  \
    CONFIG.PCW_NOR_SRAM_CS0_T_PC {1}  \
    CONFIG.PCW_NOR_SRAM_CS0_T_WP {1}  \
    CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1}  \
    CONFIG.PCW_NOR_SRAM_CS0_T_WC {11}  \
    CONFIG.PCW_NOR_SRAM_CS0_T_RC {11}  \
    CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0}  \
    CONFIG.PCW_NOR_SRAM_CS1_T_TR {1}  \
    CONFIG.PCW_NOR_SRAM_CS1_T_PC {1}  \
    CONFIG.PCW_NOR_SRAM_CS1_T_WP {1}  \
    CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1}  \
    CONFIG.PCW_NOR_SRAM_CS1_T_WC {11}  \
    CONFIG.PCW_NOR_SRAM_CS1_T_RC {11}  \
    CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0}  \
    CONFIG.PCW_NOR_CS0_T_TR {1}  \
    CONFIG.PCW_NOR_CS0_T_PC {1}  \
    CONFIG.PCW_NOR_CS0_T_WP {1}  \
    CONFIG.PCW_NOR_CS0_T_CEOE {1}  \
    CONFIG.PCW_NOR_CS0_T_WC {11}  \
    CONFIG.PCW_NOR_CS0_T_RC {11}  \
    CONFIG.PCW_NOR_CS0_WE_TIME {0}  \
    CONFIG.PCW_NOR_CS1_T_TR {1}  \
    CONFIG.PCW_NOR_CS1_T_PC {1}  \
    CONFIG.PCW_NOR_CS1_T_WP {1}  \
    CONFIG.PCW_NOR_CS1_T_CEOE {1}  \
    CONFIG.PCW_NOR_CS1_T_WC {11}  \
    CONFIG.PCW_NOR_CS1_T_RC {11}  \
    CONFIG.PCW_NOR_CS1_WE_TIME {0}  \
    CONFIG.PCW_NAND_CYCLES_T_RR {2}  \
    CONFIG.PCW_NAND_CYCLES_T_AR {2}  \
    CONFIG.PCW_NAND_CYCLES_T_CLR {1}  \
    CONFIG.PCW_NAND_CYCLES_T_WP {3}  \
    CONFIG.PCW_NAND_CYCLES_T_REA {2}  \
    CONFIG.PCW_NAND_CYCLES_T_WC {5}  \
    CONFIG.PCW_NAND_CYCLES_T_RC {5}  \
    CONFIG.PCW_SMC_CYCLE_T0 {NA}  \
    CONFIG.PCW_SMC_CYCLE_T1 {NA}  \
    CONFIG.PCW_SMC_CYCLE_T2 {NA}  \
    CONFIG.PCW_SMC_CYCLE_T3 {NA}  \
    CONFIG.PCW_SMC_CYCLE_T4 {NA}  \
    CONFIG.PCW_SMC_CYCLE_T5 {NA}  \
    CONFIG.PCW_SMC_CYCLE_T6 {NA}  \
    CONFIG.PCW_PACKAGE_NAME {clg400}  \
    CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0}  \
  ]
}

block memory generator选True Dual Port RAM(可读可写？)，然后把自己写的IP核的gmem1和gmem2按上图连接好，ctrl_0和ctrl_1的右边的端口BRAM_PORTA也连上，其他的自动布线就可以了。

之后需要设置地址：我个人认为不冲突，能在vitis中正确使用即可

之后就是常规操作，一步步生成bit文件，导出Hardware，也就是xsa文件。

打开vitis，把这个xsa文件导入，然后需要配置FATFS库，正点原子教程很详细：

2_【正点原子】领航者ZYNQ之嵌入式Vitis开发指南V1.2.pdf(官网可以下载)

完成后，依次建立以下文件，可能有的多余，没什么用，因为我遇到很多错误，踩了很多坑，所以就把他们都留着了。应该是一个main.c即可，可以尝试把没用的注释掉。

main.c

#include <stdio.h>
#include <string.h>
#include <stdlib.h> // 包含 strtol 的头文件
#include "xparameters.h"
#include "ff.h"
#include "xlenet.h"
#include "xil_printf.h"
#include "xil_cache.h"
#include "platform_config.h"

// 核心配置
#define LENET_DEVICE_ID 0
#define TARGET_DATA_CNT 784
#define OUTPUT_DATA_CNT 10
#define INPUT_BRAM_BASE XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR
#define OUTPUT_BRAM_BASE XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR
#define FILE_NAME "first_image.txt"
#define SD_PATH "0:/"

// 全局变量
FATFS fs;
XLenet Lenet_Instance;
int32_t data_array[TARGET_DATA_CNT] = {0};
u8 SD_Read_Buf[128] __attribute__ ((aligned(32)));

// 函数声明
void init_platform(void);
void cleanup_platform(void);

// SD卡挂载
void sd_mount() {
    FRESULT status = f_mount(&fs, SD_PATH, 1);
    if (status != FR_OK) {
        xil_printf("SD mount fail, formatting...\r\n");
        BYTE work[FF_MAX_SS];
        f_mkfs(SD_PATH, FM_FAT32, 0, work, sizeof(work));
        f_mount(&fs, SD_PATH, 1);
    } else xil_printf("SD mount success\r\n");
}

// SD卡读数据 - 已修改以支持十六进制格式
void sd_read_data() {
    FIL file;
    if (f_open(&file, FILE_NAME, FA_READ) != FR_OK) {
        xil_printf("Open file fail\r\n");
        return;
    }

    UINT br;
    int buf_idx=0, line_idx=0, data_cnt=0;
    char line_buf[20] = {0};

    xil_printf("SD reading data (hex format)...\r\n");
    while (data_cnt < TARGET_DATA_CNT) {
        if (buf_idx == 0) {
            memset(SD_Read_Buf, 0, sizeof(SD_Read_Buf));
            if (f_read(&file, SD_Read_Buf, sizeof(SD_Read_Buf), &br) != FR_OK || br == 0) {
                break; // 读取失败或文件结束
            }
        }

        // 遍历缓冲区内容
        while (buf_idx < br && line_idx < 19) {
            u8 c = SD_Read_Buf[buf_idx++];

            // 允许的字符：0-9, a-f, A-F, x, X, 逗号, 回车, 换行
            if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F') || c == 'x' || c == 'X' || c == ',' || c == '\r' || c == '\n') {

                if (c == ',' || c == '\r' || c == '\n') {
                    // 遇到分隔符，解析当前缓存的数字
                    line_buf[line_idx] = '\0';
                    if (strlen(line_buf) > 0) {
                        // 核心改动：使用 strtol 并指定基数为 16 来解析十六进制字符串
                        char *endptr;
                        long val = strtol(line_buf, &endptr, 16);

                        // 检查是否解析成功
                        if (endptr != line_buf) {
                            // 将解析出的值转换为 int32_t，并确保其在 0-255 范围内
                            data_array[data_cnt++] = (val > 255) ? 255 : (val < 0) ? 0 : (int32_t)val;
                        } else {
                            xil_printf("Warning: Failed to parse hex string: %s\r\n", line_buf);
                        }
                    }
                    memset(line_buf, 0, sizeof(line_buf));
                    line_idx = 0;
                } else {
                    // 否则，将字符添加到行缓冲区
                    line_buf[line_idx++] = c;
                }
            }
            // 忽略所有其他非法字符
        }
        if (buf_idx >= br) buf_idx = 0;
    }

    f_close(&file);
    xil_printf("SD read %d data entries.\r\n", data_cnt);
}


// BRAM写入+验证
void bram_write_verify() {
    xil_printf("\r\nBRAM Write & Verify (Input Addr: 0x%08X)\r\n", INPUT_BRAM_BASE);
    int32_t write_data[TARGET_DATA_CNT];
    int all_ok = 1;

    for (int i=0; i<TARGET_DATA_CNT; i++) {
        write_data[i] = data_array[i];
        Xil_Out32(INPUT_BRAM_BASE + 4*i, write_data[i]);
    }
    Xil_DCacheFlushRange(INPUT_BRAM_BASE, TARGET_DATA_CNT*4);
    xil_printf("BRAM write complete (cache flushed)\r\n");

    int test_indices[] = {2, 50, 100, 200, 300, 783}; // 增加一个末尾元素的验证
    for (int k=0; k<sizeof(test_indices)/sizeof(test_indices[0]); k++) {
        int i = test_indices[k];
        if (i >= TARGET_DATA_CNT) continue;
        int32_t read_val = Xil_In32(INPUT_BRAM_BASE + 4*i);
        if (write_data[i] != read_val) {
            xil_printf("BRAM[%d] Verify FAIL: write=%d (0x%02X), read=%d (0x%02X)\r\n",
                       i, write_data[i], write_data[i], read_val, read_val);
            all_ok = 0;
        }
    }
    xil_printf(all_ok ? "BRAM Verify: ALL PASS\r\n" : "BRAM Verify: FAIL\r\n");
}

// IP核运行
void lenet_run() {
    XLenet_Config *cfg = XLenet_LookupConfig(LENET_DEVICE_ID);
    if (!cfg || XLenet_CfgInitialize(&Lenet_Instance, cfg) != XST_SUCCESS) {
        xil_printf("IP init fail\r\n");
        return;
    }
    XLenet_Start(&Lenet_Instance);
    xil_printf("IP started, waiting for finish...\r\n");
    while (XLenet_IsDone(&Lenet_Instance) == 0);
}

//读取输出结果
void read_output() {
    printf("\r\nLeNet Output:\r\n");

    for (int i = 0; i < OUTPUT_DATA_CNT; i++) {
        u32 data_address = OUTPUT_BRAM_BASE + i * 4;
        u32 raw_data = Xil_In32(data_address);

        // 将32位整数按位解释为float
        float output_val = *(float*)&raw_data;

        printf("Output[%d] - Addr: 0x%08X, Raw: 0x%08X, Value: %.6f\r\n",
               i, data_address, raw_data, output_val);
    }
}

int main() {
    init_platform();
    xil_printf("================ LeNet FPGA ================\r\n");
    xil_printf("Target file: %s\r\n", FILE_NAME);

    sd_mount();
    sd_read_data();
    bram_write_verify();
    lenet_run();
    read_output();

    xil_printf("================ All Done ================\r\n");
    cleanup_platform();
    return 0;
}

platform.c

/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

#include "xparameters.h"
#include "xil_cache.h"

#include "platform_config.h"

/*
 * Uncomment one of the following two lines, depending on the target,
 * if ps7/psu init source files are added in the source directory for
 * compiling example outside of SDK.
 */
/*#include "ps7_init.h"*/
/*#include "psu_init.h"*/

#ifdef STDOUT_IS_16550
 #include "xuartns550_l.h"

 #define UART_BAUD 9600
#endif

void
enable_caches()
{
#ifdef __PPC__
    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
    Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
    Xil_DCacheEnable();
#endif
#endif
}

void
disable_caches()
{
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
    Xil_DCacheDisable();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
    Xil_ICacheDisable();
#endif
#endif
}

void
init_uart()
{
#ifdef STDOUT_IS_16550
    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
    /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
}

void
init_platform()
{
    /*
     * If you want to run this example outside of SDK,
     * uncomment one of the following two lines and also #include "ps7_init.h"
     * or #include "ps7_init.h" at the top, depending on the target.
     * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
     * along with this example source files for compilation.
     */
    /* ps7_init();*/
    /* psu_init();*/
    enable_caches();
    init_uart();
}

void
cleanup_platform()
{
    disable_caches();
}

platform.h

/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

#ifndef __PLATFORM_H_
#define __PLATFORM_H_

#include "platform_config.h"

void init_platform();
void cleanup_platform();

#endif

platform_config.h

#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_

#define STDOUT_IS_PS7_UART
#define UART_DEVICE_ID 0
#endif

sd卡中存放的数据类型是这种形式的：

0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xb5,
0xa8,
0xa2,
0xa6,
0xa3

上板验证：

跟HLS中的仿真不完全一样，但如果加一个softmax的话，输出类别是一致的，应该是问题不大。

整体过程我感觉很费时间，好几次打印出来的数值是空或NAN，必须要去HLS中去修改，只能说牵一发而动全身，建议有错误时先把HLS中关于卷积全连接计算的代码先注释掉，只保留输入输出，看IP核是否正常工作，是否sd卡能正确读数据到bram0，IP核能否从bram0读数并传数据到bram1，PS端能否从bram1读数据并在串口打印？

再以整体流程结尾吧，作为初学者现在对FPGA知之甚少，我的任务应该是需要在FPGA上部署目标检测相关模型，网上相关开源资料甚少，希望大家能多交流，多开源吧。